1. Field of the Invention
The present invention relates to a power amplifier using a plurality of transistors and a chip carrier on which a plurality of transistor chips are mounted.
2. Description of the Related Art
Power amplifiers using a plurality of transistors are used in transmitting/receiving devices for use in microwave communication systems, for example. FIG. 21 is a circuit diagram showing an example of a conventional power amplifier using a plurality of MESFETs (Metal Semiconductor Field-Effect Transistors, referred to simply as EFT hereinafter).
The power amplifier shown in FIG. 21 includes four FETs 1, a divider 41, a first matching circuit 42, a second matching circuit 51, and a combiner 52.
The four chips of the FETs 1 are mounted on a chip carrier 60. A plurality of .lambda./8 lines SL1, SL3, a plurality of capacitors CA, C1, and a resistor R are provided on a substrate 40. A plurality of .lambda./8 lines SL2, SL4, SL7 and a plurality of capacitors CB, C2 are provided on a substrate 50.
An input pad PI on the substrate 40 is connected to a node NI through the capacitor C1 and the resistor R is connected between the node NI and a gate-bias Pad PVg. Connected to the gate-bias pad PVg are a gate-bias power-supply Vg and a capacitor Cg for stabilization of the power-supply voltage.
The node NI is connected to two nodes N1 through the two .lambda./8 lines SL3. Each node N1 is connected to two pads PA through two .lambda./8 lines SL1. Each pad PA is grounded through a capacitor CA. Each pad PA is connected to the gate of each FET 1 through a bonding wire BWA.
An output pad PO on the substrate 50 is connected to a node NO through the capacitor C2 and the node NO is connected to a drain-bias pad PVd through the .lambda./4 line SL7. Connected to the drain-bias pad PVd are a drain-bias power-supply Vd, an end of the .lambda./4 line SL7, and a capacitor Cd for stabilization of the power-supply voltage.
The node NO is connected to two nodes N2 through the two .lambda./8 lines SL4. Each of the nodes N2 is connected to two pads PB through two .lambda./8 lines SL2. Each of the pads PB is grounded through each capacitor CB. Each pad PB is connected to the drain of each FET 1 through a bonding wire BWB.
The .lambda./8 lines SL3, SL1 on the substrate 40 form the divider 41 and the capacitors CA and the bonding wires BWA form the matching circuit 42. The bonding wires BWB and the capacitors CB form the matching circuit 51 and the .lambda./8 lines SL2, SL4 on the substrate 50 form the combiner 52.
A gate bias is applied to the gate of each FET 1 from the gate-bias power-supply Vg through the .lambda./8 lines SL3, SL1 in the divider 41 and the bonding wires BWA. A drain bias is applied to the drain of each FET 1 from the drain-bias power-supply Vd through the .lambda./8 lines SL4, SL2 in the combiner 52 and the bonding wires BWB.
An RF signal (high-frequency signal) applied to the input pad PI is distributed by the divider 41 and applied to the gates of the four FETs 1, and the RF signals amplified in the FETs 1 are outputted from their respective drains. The RF signals outputted from the drains of the four FETs 1 are combined in the combiner 52 and outputted from the output pad PO. The matching circuit 42 obtains an impedance match between the divider 41 and each FET 1 and the matching circuit 51 obtains an impedance match between each FET 1 and the combiner 52.
In the above-described conventional power amplifier, the drain bias is applied to the drains of the plurality of FETs 1 through the .lambda./8 lines SL4, SL2 in the combiner 52 and the bonding wires BWB. In this case, since the .lambda./8 lines SL4, SL2 have a resistance component, the drain current causes a voltage drop, which leads to large loss.
Further, since the bonding wires BWB form the matching circuit 51, it is not possible to arbitrarily increase the number of the bonding wires BWB. Then the bonding wires BWB may be disconnected if an overcurrent flows therethrough. Moreover, it is not easy to arbitrarily adjust the value of the inductor (wire inductor) of the bonding wires BWB, leading to difficulties in designing and adjusting the matching circuit 51. Furthermore, if the plurality of FETs 1 have variations in gate capacitance, it is likely to cause low-frequency oscillation.